Invention Grant
US08230378B2 Method for IC wiring yield optimization, including wire widening during and after routing
有权
IC布线产量优化方法,包括布线期间和之后的线宽
- Patent Title: Method for IC wiring yield optimization, including wire widening during and after routing
- Patent Title (中): IC布线产量优化方法,包括布线期间和之后的线宽
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Application No.: US12572297Application Date: 2009-10-02
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Publication No.: US08230378B2Publication Date: 2012-07-24
- Inventor: John M. Cohn , Jason D. Hibbeler , Gustavo E. Tellez
- Applicant: John M. Cohn , Jason D. Hibbeler , Gustavo E. Tellez
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Gibb I.P. Law Firm, LLC
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Disclosed are embodiments of a method, service, and computer program product for performing yield-aware IC routing for a design. The method performs an initial global routing which satisfies wiring congestion constraints. Next, the method performs wire spreading and wire widening on the global route, layer by layer, based on, for example, a quadratic congestion optimization. Following this, timing closure is performed on the global route using results of the wire spreading and wire widening. Post-routing wiring width and wire spreading adjustments are made using the critical area yield model. In addition, the method allows for the optimization of already-routed data.
Public/Granted literature
- US20100023913A1 METHOD FOR IC WIRING YIELD OPTIMIZATION, INCLUDING WIRE WIDENING DURING AND AFTER ROUTING Public/Granted day:2010-01-28
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