Invention Grant
- Patent Title: Trace reconstruction for silicon validation of asynchronous systems-on-chip
- Patent Title (中): 异步系统芯片的硅验证跟踪重构
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Application No.: US12611156Application Date: 2009-11-03
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Publication No.: US08234618B2Publication Date: 2012-07-31
- Inventor: Mrinal Bose , Jayanta Bhadra , Hillel Miller , Edward L. Swarthout , Ekaterina A. Trofimova
- Applicant: Mrinal Bose , Jayanta Bhadra , Hillel Miller , Edward L. Swarthout , Ekaterina A. Trofimova
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agency: Van Leeuwen & Van Leeuwen
- Agent Joanna Chiu
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F11/00

Abstract:
A test system collects passing event data and failing event data, and merges the collected data into passing subsequences and failing subsequences, respectively. The test system identifies an overlap area between the passing subsequence and the failing subsequence in regards to time slices and tracepoint slices, and creates passing transactions and failing transactions using the event data corresponding to the overlap area. Next, the test system detects a timing discrepancy between the first passing transaction relative to the second passing transaction compared with the first failing transaction relative to the second failing transaction. The test system then reports the detected timing discrepancy, which allows a test engineer to perturb the test program in order to more frequently catch intermittent failures caused by asynchronous timing conditions.
Public/Granted literature
- US20110107146A1 Trace Reconstruction for Silicon Validation of Asynchronous Systems-on-Chip Public/Granted day:2011-05-05
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