Invention Grant
- Patent Title: Fully isolated high-voltage MOS device
- Patent Title (中): 全隔离高压MOS器件
-
Application No.: US12910591Application Date: 2010-10-22
-
Publication No.: US08236642B2Publication Date: 2012-08-07
- Inventor: Chi-San Wei , Kuo-Ming Wu , Yi-Chun Lin
- Applicant: Chi-San Wei , Kuo-Ming Wu , Yi-Chun Lin
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L21/02
- IPC: H01L21/02

Abstract:
A semiconductor structure includes a semiconductor substrate; an n-type tub extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the n-type tub comprises a bottom buried in the semiconductor substrate; a p-type buried layer (PBL) on a bottom of the tub, wherein the p-type buried layer is buried in the semiconductor substrate; and a high-voltage n-type metal-oxide-semiconductor (HVNMOS) device over the PBL and within a region encircled by sides of the n-type tub.
Public/Granted literature
- US20110039387A1 Fully Isolated High-Voltage MOS Device Public/Granted day:2011-02-17
Information query
IPC分类: