发明授权
US08238191B2 Dual port PLD embedded memory block to support read-before-write in one clock cycle 失效
双端口PLD嵌入式内存块,支持在一个时钟周期内进行预写入

  • 专利标题: Dual port PLD embedded memory block to support read-before-write in one clock cycle
  • 专利标题(中): 双端口PLD嵌入式内存块,支持在一个时钟周期内进行预写入
  • 申请号: US12687823
    申请日: 2010-01-14
  • 公开(公告)号: US08238191B2
    公开(公告)日: 2012-08-07
  • 发明人: Haiming Yu
  • 申请人: Haiming Yu
  • 申请人地址: US CA San Jose
  • 专利权人: Altera Corporation
  • 当前专利权人: Altera Corporation
  • 当前专利权人地址: US CA San Jose
  • 代理机构: Womble Carlyle Sandridge & Rice, LLP
  • 主分类号: G11C8/00
  • IPC分类号: G11C8/00
Dual port PLD embedded memory block to support read-before-write in one clock cycle
摘要:
A method for a read-before-write functionality for a memory within a programmable logic device (PLD) is provided. The method begins when a read operation and a write operation are initiated through two different ports of a memory simultaneously to access the same address in the memory. In order to prevent the write operation from proceeding prior to the read operation, a read-before-write control logic is provided to the control block of the port that supports the write operation. Thus, the write operation is paused until the control block of the port that supports the write operation receives a signal from a read sense amplifier indicating that the read operation is complete. The read sense amplifier is capable of detecting the completion of a read operation by monitoring the voltage difference of the read bitline. When this voltage difference reaches a threshold value, the read sense amplifier triggers a write wordline signal. The enabling of the write wordline signal causes, the data to be written to the memory.
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