发明授权
US08244512B1 Method and apparatus for simulating a circuit using timing insensitive glitch-free (TIGF) logic
有权
用于使用时序不敏感无毛刺（TIGF）逻辑模拟电路的方法和装置
- 专利标题： Method and apparatus for simulating a circuit using timing insensitive glitch-free (TIGF) logic
- 专利标题（中）： 用于使用时序不敏感无毛刺（TIGF）逻辑模拟电路的方法和装置
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申请号： US09954989申请日： 2001-09-12
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公开(公告)号： US08244512B1公开(公告)日： 2012-08-14
- 发明人: Ping-Sheng Tseng , Sharon Sheau-Pyng Lin , Quincy Kun-Hsu Shen , Mike Mon Yen Tsai , Steven Wang
- 申请人： Ping-Sheng Tseng , Sharon Sheau-Pyng Lin , Quincy Kun-Hsu Shen , Mike Mon Yen Tsai , Steven Wang
- 申请人地址： US CA San Jose
- 专利权人： Cadence Design Systems, Inc.
- 当前专利权人： Cadence Design Systems, Inc.
- 当前专利权人地址： US CA San Jose
- 代理机构： Holland & Knight LLP
- 代理商 Brian J. Colandreo, Esq.; Mark H. Whittenberger, Esq.
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
The debug system described in this patent specification provides a system that generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device. This particular FPGA device is called a Behavior Processor. This Behavior Processor executes in hardware those code constructs that were previously executed in software. When some condition is satisfied (e.g., If . . . then . . . else loop) which requires some intervention by the workstation or the software model, the Behavior Processor works with an Xtrigger device to send a callback signal to the workstation for immediate response.
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