Invention Grant
- Patent Title: Dual interlayer dielectric stressor integration with a sacrificial underlayer film stack
- Patent Title (中): 双层电介质应力集成与牺牲底层膜堆叠
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Application No.: US11650252Application Date: 2007-01-04
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Publication No.: US08247850B2Publication Date: 2012-08-21
- Inventor: Dharmesh Jawarani , Ross E. Noble , David C. Wang
- Applicant: Dharmesh Jawarani , Ross E. Noble , David C. Wang
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agency: Jackson Walker L.L.P.
- Main IPC: H01L29/76
- IPC: H01L29/76
Abstract:
A method for making a semiconductor device is provided by (a) providing a substrate (203) having first (205) and second (207) gate structures thereon; (b) forming an underlayer (231) over the first and second gate structures; (c) removing the underlayer from the first gate structure; (d) forming a first stressor layer (216) over the first and second gate structures; and (e) selectively removing the first stressor layer from the second gate structure through the use of a first etch which is selective to the underlayer.
Public/Granted literature
- US20080164531A1 Dual interlayer dielectric stressor integration with a sacrificial underlayer film stack Public/Granted day:2008-07-10
Information query
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