发明授权
- 专利标题: Protection of integrated circuit gates during metallization processes
- 专利标题(中): 在金属化过程中保护集成电路门
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申请号: US11411064申请日: 2006-04-25
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公开(公告)号: US08264043B1公开(公告)日: 2012-09-11
- 发明人: Sanjay Rekhi , Nagendra Cherukupalli , Paul D. Keswick
- 申请人: Sanjay Rekhi , Nagendra Cherukupalli , Paul D. Keswick
- 申请人地址: US CA San Jose
- 专利权人: Cypress Semiconductor Corporation
- 当前专利权人: Cypress Semiconductor Corporation
- 当前专利权人地址: US CA San Jose
- 主分类号: H01L23/60
- IPC分类号: H01L23/60
摘要:
In one embodiment, a first transistor is configured to switch ON to discharge accumulated charges on an interconnect line during a metallization process. This advantageously protects a second transistor, which is coupled to the interconnect line, from charge buildup. The gate of the first transistor may be coupled to the interconnect line by way of a coupling capacitor. The gate of the first transistor may remain floating during the metallization process, and subsequently coupled to ground at a topmost metal level. The metallization process may be physical vapor deposition, for example.
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