发明授权
US08266498B2 Implementation of multiple error detection schemes for a cache 有权
实现高速缓存的多个错误检测方案

  • 专利标题: Implementation of multiple error detection schemes for a cache
  • 专利标题(中): 实现高速缓存的多个错误检测方案
  • 申请号: US12415672
    申请日: 2009-03-31
  • 公开(公告)号: US08266498B2
    公开(公告)日: 2012-09-11
  • 发明人: William C. Moyer
  • 申请人: William C. Moyer
  • 申请人地址: US TX Austin
  • 专利权人: Freescale Semiconductor, Inc.
  • 当前专利权人: Freescale Semiconductor, Inc.
  • 当前专利权人地址: US TX Austin
  • 代理商 David G. Dolezal; Joanna G. Chiu
  • 主分类号: G06F11/00
  • IPC分类号: G06F11/00
Implementation of multiple error detection schemes for a cache
摘要:
A cache includes a plurality of cache lines, where each cache line includes a detection type field, corresponding cache data field, a detection field, and a corresponding tag field. The detection type field indicates an error detection scheme from a plurality of error detection schemes currently in use for the corresponding cache data field. One example of an error detection scheme is a multiple bit error detection scheme (e.g. an error detection coding (EDC) or an error correction coding (ECC)). Another type is a single bit error detection scheme (e.g. parity error detection). The detection bits field stores parity bits if parity error detection is used. The detection bits field stores checking bits if EDC coding is used.
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