Invention Grant
- Patent Title: Delay circuit
- Patent Title (中): 延时电路
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Application No.: US12745350Application Date: 2008-12-02
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Publication No.: US08269553B2Publication Date: 2012-09-18
- Inventor: Kazuhiro Yamamoto , Toshiyuki Okayasu
- Applicant: Kazuhiro Yamamoto , Toshiyuki Okayasu
- Applicant Address: JP Tokyo
- Assignee: Advantest Corporation
- Current Assignee: Advantest Corporation
- Current Assignee Address: JP Tokyo
- Agency: Ladas & Parry, LLP
- Priority: JP2007-313796 20071204
- International Application: PCT/JP2008/003559 WO 20081202
- International Announcement: WO2009/072268 WO 20090611
- Main IPC: H01L25/00
- IPC: H01L25/00

Abstract:
A delay circuit includes a MOSFET and bias voltage sources. The bias voltage sources apply a voltage difference between the drain and source of the MOSFET. The bias voltage source supplies a source voltage to a source electrode of the MOSFET. The bias voltage source supplies a drain voltage to a drain electrode of the MOSFET. An input signal to be delayed is propagated through the gate of the MOSFET in the gate width direction (y-axis direction).
Public/Granted literature
- US20100259435A1 DELAY CIRCUIT Public/Granted day:2010-10-14
Information query
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