发明授权
US08271925B2 Printed board design system and method including decoupling capacitor arrangement examination unit
有权
印刷电路板设计系统及方法,包括去耦电容布置检查单元
- 专利标题: Printed board design system and method including decoupling capacitor arrangement examination unit
- 专利标题(中): 印刷电路板设计系统及方法,包括去耦电容布置检查单元
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申请号: US12628350申请日: 2009-12-01
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公开(公告)号: US08271925B2公开(公告)日: 2012-09-18
- 发明人: Naoki Kobayashi
- 申请人: Naoki Kobayashi
- 申请人地址: JP Tokyo
- 专利权人: NEC Corporation
- 当前专利权人: NEC Corporation
- 当前专利权人地址: JP Tokyo
- 优先权: JP2008-306250 20081201
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
A decoupling capacitor pin position information obtain unit calculates based on board design data of a printed board, position information indicating positions of decoupling capacitors on the printed board. A power supply plane position/shape information obtain unit calculates based on the board design data, position/shape information indicating a position and shape of a power supply plane of the printed board. A restriction condition input unit collects restriction conditions from an input device. A decoupling capacitor examination unit judges based on the position information, the position/shape information and the restriction conditions, whether or not arrangement of the decoupling capacitors is adequate. Therefore, a designer, while designing arrangement/wiring of the printed board, can check in real time whether or not the arrangement of the decoupling capacitors is adequate, and thus can design at higher speed a printed board in which arrangement of decoupling capacitors is adequate.
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