Invention Grant
US08278146B2 Manufacturing method of chip package with coplanarity controlling feature
有权
具有共面性控制特性的芯片封装制造方法
- Patent Title: Manufacturing method of chip package with coplanarity controlling feature
- Patent Title (中): 具有共面性控制特性的芯片封装制造方法
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Application No.: US12330143Application Date: 2008-12-08
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Publication No.: US08278146B2Publication Date: 2012-10-02
- Inventor: Jing-en Luan
- Applicant: Jing-en Luan
- Applicant Address: SG Singapore
- Assignee: STMicroelectronics Asia Pacific Pte Ltd
- Current Assignee: STMicroelectronics Asia Pacific Pte Ltd
- Current Assignee Address: SG Singapore
- Agency: Seed IP Law Group PLLC
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/28 ; H01L23/48 ; H01L23/482 ; H01L25/16
Abstract:
A chip package includes a substrate, an integrated circuit proximate a top surface of the substrate, and a cap comprising encapsulant that encapsulates the integrated circuit on at least a portion of the top surface of the substrate. The chip package further includes at least one extension feature positioned on at least a portion of the top surface of the substrate. The at least one extension feature also comprises the encapsulant and extends from the cap to a perimeter of the substrate.
Public/Granted literature
- US20100140810A1 CHIP PACKAGE WITH COPLANARITY CONTROLLING FEATURE Public/Granted day:2010-06-10
Information query
IPC分类:
