发明授权
- 专利标题： Packed restricted floating point representation and logic for conversion to single precision float
- 专利标题（中）： 封装的限制浮点表示和逻辑转换为单精度浮点数
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申请号： US11648265申请日： 2006-12-29
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公开(公告)号： US08280936B2公开(公告)日： 2012-10-02
- 发明人: Hong Jiang
- 申请人： Hong Jiang
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Trop, Pruner & Hu, P.C.
- 主分类号： G06F7/00
- IPC分类号： G06F7/00 ; G06F15/00 ; G06F7/38 ; H03M7/00
摘要：
An apparatus for expanding an immediate vector of restricted data structures may include logic connected to a first memory and a second memory connected to the logic. The first memory may store the immediate vector of restricted data structures that specify distinct floating point numbers. The immediate vector may have a fixed number of bits. The logic may expand the vector of restricted data structures into a number of corresponding expanded data structures that also specify the distinct floating point numbers. Each of the expanded data structures may also have the fixed number of bits. The second memory may store the number of corresponding expanded data structures.
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