发明授权
- 专利标题： High voltage tolerant bus holder circuit and method of operating the circuit
- 专利标题（中）： 高耐压母线电路和操作电路的方法
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申请号： US13152764申请日： 2011-06-03
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公开(公告)号： US08283947B1公开(公告)日： 2012-10-09
- 发明人: Jayarama Ubaradka , Dharmaray M. Nedalgi
- 申请人： Jayarama Ubaradka , Dharmaray M. Nedalgi
- 申请人地址： NL Eindhoven
- 专利权人： NXP B.V.
- 当前专利权人： NXP B.V.
- 当前专利权人地址： NL Eindhoven
- 主分类号： H03K19/0175
- IPC分类号： H03K19/0175
摘要：
A high voltage tolerant bus holder circuit and method of operating the bus holder circuit utilizes first and second control transistors connected in parallel between a control terminal of a pull-up transistor and a bus. The first control transistor is used to turn on the pull-up transistor during a pull-up mode of operation. The second control transistor is used to turn off the pull-down transistor when a voltage on the bus exceeds a threshold.
信息查询
IPC分类:
