As part of the design process it is required to design circuits in order to reduce their power consumption. This is typically done by enabling or disabling flip-flops (FFs), however, such change in the circuit requires certain verification. As sequential clock gating changes the state function it is necessary to perform a sequential equivalence checking (SEC) verification. Applying a full SEC may be runtime consuming and is not scalable for large designs. Methods to reduce the problem of verifying sequential clock gating by reducing the sequential problem into much smaller problem that can be easily solved is therefore shown.