Invention Grant
US08285903B2 Requests and data handling in a bus architecture 有权
总线架构中的请求和数据处理

Requests and data handling in a bus architecture
Abstract:
The present invention relates to improved methods for processing requests and sending data in a bus architecture. The present invention further relates to an improved bus architecture for processing requests and data. There is provided a method for processing read requests in a bus architecture comprising at least one master device connected to at least two slave devices via a bus. The architecture comprises an allocator for allocating incoming requests from the master device to a target slave device and an optimiser for each slave device. Each optimiser is for buffering incoming requests for the respective slave device. The method comprising the steps of: a) the master device sending a read request for a first slave device to the bus; b) the allocator generating a current-state indicator associated with the read request. The current-state indicator has an initial value, The method further comprises c) the allocator generating a priority indicator associated with the read request; d) the allocator sending the read request, the current-state indicator and the priority indicator to the optimiser of the first slave device; e) the optimiser of the first slave device receiving the read request, the current-state indicator and the priority indicator. Finally, if the initial value of the current-state indicator equals the value of the priority indicator, the method comprises processing the read request; or if the initial value of the current-state indicator does not equal the value of priority indicator, the method comprises deferring processing of the read request until a later time.
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