Invention Grant
- Patent Title: Package substrate
- Patent Title (中): 封装衬底
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Application No.: US12814102Application Date: 2010-06-11
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Publication No.: US08289727B2Publication Date: 2012-10-16
- Inventor: Chin-Sung Lin , Li-Hua Lin , Yu-Yu Lin
- Applicant: Chin-Sung Lin , Li-Hua Lin , Yu-Yu Lin
- Applicant Address: TW Hsin-Chu TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.,Global Unichip Corp.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.,Global Unichip Corp.
- Current Assignee Address: TW Hsin-Chu TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H05K7/00
- IPC: H05K7/00 ; H05K1/11

Abstract:
In accordance with an embodiment, a substrate layout comprises a ground plane of a first power loop on a layer of a substrate, a first trace rail on the layer extending along a first periphery of the ground plane, and a first perpendicular trace coupled to the first trace rail. The ground plane is between the first trace rail and a die area, and the first perpendicular trace extends perpendicularly from the first trace rail. The first trace rail and the first perpendicular trace are components of a second power loop.
Public/Granted literature
- US20110304998A1 Package Substrate Public/Granted day:2011-12-15
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