A processing unit includes a processor core and a cache memory coupled to the processor core. The cache memory includes a data array, a directory of the data array, error detection logic that sequentially detects a first, second and third correctable errors in the data array of the cache memory and provides indications of detection of the first, second and third correctable errors, and control circuitry that, responsive to the indication of the third correctable error and an indication that the first and second correctable errors occurred at too high a frequency, marks an entry of the data array containing a cache line having the third correctable error as deleted in the directory of the cache memory regardless of which entry of the data array contains a cache line having the second correctable error.