发明授权
- 专利标题: Parity generator, priority encoder, and information processor
- 专利标题(中): 奇偶校验发生器,优先编码器和信息处理器
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申请号: US12181521申请日: 2008-07-29
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公开(公告)号: US08291307B2公开(公告)日: 2012-10-16
- 发明人: Moriyuki Santou
- 申请人: Moriyuki Santou
- 申请人地址: JP Kawasaki
- 专利权人: Fujitsu Limited
- 当前专利权人: Fujitsu Limited
- 当前专利权人地址: JP Kawasaki
- 代理机构: Staas & Halsey LLP
- 主分类号: G06F11/00
- IPC分类号: G06F11/00
摘要:
In order to generate a parity of output data from a priority encoder without increasing processing time or making the circuitry complex, the present invention a first level generator having a plurality of first component circuits arranged in parallel, into each of which one of a plurality of sets of a specific number of bits of the binary data in sequence from the most significant bit is input and each of which generates and outputs a first signal for parity generation of bit data of the specific number of bits and a second signal representing whether or not the entire bit data of the specific number of bits is “0s” or “1s”; and a second level generator generating the parity of the binary data based on the first signal and the second signal from each of said first component circuits of said first level generator.
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