Invention Grant
- Patent Title: Method for forming fine pattern in semiconductor device
- Patent Title (中): 在半导体器件中形成精细图案的方法
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Application No.: US12618530Application Date: 2009-11-13
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Publication No.: US08293458B2Publication Date: 2012-10-23
- Inventor: Jun-Gyeong Lee , Jung-Youl Lee , Jeong-Sik Kim , Eu-Jean Jang , Jae-Woo Lee , Deog-Bae Kim , Jae-Hyun Kim
- Applicant: Jun-Gyeong Lee , Jung-Youl Lee , Jeong-Sik Kim , Eu-Jean Jang , Jae-Woo Lee , Deog-Bae Kim , Jae-Hyun Kim
- Applicant Address: KR
- Assignee: Dongjin Semichem .Co., Ltd.
- Current Assignee: Dongjin Semichem .Co., Ltd.
- Current Assignee Address: KR
- Agency: Park & Associates IP Law, P.C.
- Priority: KR10-2009-0020837 20090311
- Main IPC: G03F7/00
- IPC: G03F7/00 ; G03F7/004 ; G03F7/40

Abstract:
Disclosed is a method for manufacturing fine patterns of semiconductor devices using a double exposure patterning process for manufacturing the second photoresist patterns by simply exposing without an exposure mask. The method comprises the steps of: forming a first photoresist pattern on a semiconductor substrate on which a layer to be etched is formed; coating a composition for a mirror interlayer on the first photoresist pattern to form a mirror interlayer; forming a photoresist layer on the resultant; and forming a second photoresist pattern which is made by a scattered reflection of the mirror-interlayer and positioned between the first photoresist patterns, by exposing the photoresist layer to a light having energy which is lower than a threshold energy (Eth) of the photoresist layer without an exposure mask, and then developing the same.
Public/Granted literature
- US20100233622A1 METHOD FOR FORMING FINE PATTERN IN SEMICONDUCTOR DEVICE Public/Granted day:2010-09-16
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