Invention Grant
US08293587B2 Multilayer pillar for reduced stress interconnect and method of making same
有权
用于减少应力互连的多层支柱及其制造方法
- Patent Title: Multilayer pillar for reduced stress interconnect and method of making same
- Patent Title (中): 用于减少应力互连的多层支柱及其制造方法
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Application No.: US11870583Application Date: 2007-10-11
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Publication No.: US08293587B2Publication Date: 2012-10-23
- Inventor: Virendra R Jadhav , Krystyna W Semkow , Kamalesh K Srivastava , Brian R Sundlof
- Applicant: Virendra R Jadhav , Krystyna W Semkow , Kamalesh K Srivastava , Brian R Sundlof
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Roberts, Mlotkowski, Safran & Cole, P.C.
- Agent Joseph Petrokaitis
- Main IPC: H01L21/00
- IPC: H01L21/00
Abstract:
A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
Public/Granted literature
- US20090095502A1 MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAKING SAME Public/Granted day:2009-04-16
Information query
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