Invention Grant
US08296702B2 Rectilinear covering method with bounded number of rectangles for designing a VLSI chip
失效
用于设计VLSI芯片的有限数量的矩形的直线覆盖方法
- Patent Title: Rectilinear covering method with bounded number of rectangles for designing a VLSI chip
- Patent Title (中): 用于设计VLSI芯片的有限数量的矩形的直线覆盖方法
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Application No.: US12686412Application Date: 2010-01-13
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Publication No.: US08296702B2Publication Date: 2012-10-23
- Inventor: Maharaj Mukherjee
- Applicant: Maharaj Mukherjee
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent H. Daniel Schnurmann
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method for creating a rectilinear non-convex polygonal output representative of a component used to build a VLSI circuit chip from a plurality of points corresponding to a plurality of components of the chip includes: covering the plurality of points with a set of rectangles; creating a Voronoi diagram for the set of rectangles; forming a nearest neighbor tree for the Voronoi diagram; connecting a selected set of the rectangles corresponding to the nearest neighbor tree into a non-convex rectilinear polygon; and applying the non-convex rectilinear polygon to build the VLSI chip.
Public/Granted literature
- US20110173579A1 Rectilinear Covering Method With Bounded Number of Rectangles for Designing a VLSI Chip Public/Granted day:2011-07-14
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