发明授权
- 专利标题： Constraint minimization method for formal verification
- 专利标题（中）： 用于形式验证的约束最小化方法
-
申请号： US12831497申请日： 2010-07-07
-
公开(公告)号： US08316332B1公开(公告)日： 2012-11-20
- 发明人: Pradeep Goyal , Alok Jain
- 申请人： Pradeep Goyal , Alok Jain
- 申请人地址： US CA San Jose
- 专利权人： Cadence Design Systems, Inc.
- 当前专利权人： Cadence Design Systems, Inc.
- 当前专利权人地址： US CA San Jose
- 代理机构： Holland & Knight LLP
- 代理商 Brian J. Colandreo, Esq.; Mark H. Whittenberger, Esq.
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
The present disclosure relates to a method for minimizing constraints in the formal verification of an integrated circuit design. The method may include obtaining an unisolated list of constraints initially comprising all known constraints for the integrated circuit design and obtaining an isolated list of constraints initially comprising none of the known constraints. The method may further include attempting to prove an assertion without the known constraints and determining if the assertion is valid. The method may further include updating the isolated list of constraints.
信息查询
