发明授权
US08329559B2 Damascene process for use in fabricating semiconductor structures having micro/nano gaps
有权
用于制造具有微/纳米间隙的半导体结构的镶嵌工艺
- 专利标题： Damascene process for use in fabricating semiconductor structures having micro/nano gaps
- 专利标题（中）： 用于制造具有微/纳米间隙的半导体结构的镶嵌工艺
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申请号： US11737545申请日： 2007-04-19
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公开(公告)号： US08329559B2公开(公告)日： 2012-12-11
- 发明人: Hideki Takeuchi , Emmanuel P. Quevy , Tsu-Jae King , Roger T. Howe
- 申请人： Hideki Takeuchi , Emmanuel P. Quevy , Tsu-Jae King , Roger T. Howe
- 申请人地址： US CA Oakland
- 专利权人： The Regents of the University of California
- 当前专利权人： The Regents of the University of California
- 当前专利权人地址： US CA Oakland
- 代理商 John P. O'Banion
- 主分类号： H01L21/46
- IPC分类号： H01L21/46 ; H01L21/78 ; H01L21/301
摘要：
In fabricating a microelectromechanical structure (MEMS), a method of forming a narrow gap in the MEMS includes a) depositing a layer of sacrificial material on the surface of a supporting substrate, b) photoresist masking and at least partially etching the sacrificial material to form at least one blade of sacrificial material, c) depositing a structural layer over the sacrificial layer, and d) removing the sacrificial layer including the blade of the sacrificial material with a narrow gap remaining in the structural layer where the blade of sacrificial material was removed.
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