Certain embodiments provide an ADC includes a comparator, a binary counter and a control circuit. The comparator compares a first analog signal voltage with a first reference voltage, and compares a second analog signal voltage with a second reference voltage. The binary counter counts up the clock signal for a first period until the first reference voltage becomes equal to the first analog signal after the comparator starts to compare the first reference voltage with the first analog signal voltage, and inverts a logic level of the count output having a plurality of bits after the first period elapses. The binary counter counts up the clock signal for a second period until the second reference voltage becomes equal to a second analog signal after the comparator starts to compare the second reference voltage with the second analog signal voltage.