发明授权
US08338314B2 Technique for reducing topography-related irregularities during the patterning of a dielectric material in a contact level of closely spaced transistors
失效
在紧密间隔的晶体管的接触电平中的介电材料的图案化期间减小与形貌相关的不规则性的技术
- 专利标题： Technique for reducing topography-related irregularities during the patterning of a dielectric material in a contact level of closely spaced transistors
- 专利标题（中）： 在紧密间隔的晶体管的接触电平中的介电材料的图案化期间减小与形貌相关的不规则性的技术
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申请号： US12372006申请日： 2009-02-17
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公开(公告)号： US08338314B2公开(公告)日： 2012-12-25
- 发明人: Ralf Richter , Heike Salz , Robert Seidel
- 申请人： Ralf Richter , Heike Salz , Robert Seidel
- 申请人地址： US TX Austin
- 专利权人： Advanced Micro Devices, Inc.
- 当前专利权人： Advanced Micro Devices, Inc.
- 当前专利权人地址： US TX Austin
- 代理机构： Williams, Morgan & Amerson, P.C.
- 优先权： DE102008021555 20080430
- 主分类号： H01L21/31
- IPC分类号： H01L21/31
摘要：
In a dual stress liner approach, the surface conditions after the patterning of a first stress-inducing layer may be enhanced by appropriately designing an etch sequence for substantially completely removing an etch stop material, which may be used for the patterning of the second stress-inducing dielectric material, while, in other cases, the etch stop material may be selectively formed after the patterning of the first stress-inducing dielectric material. Hence, the dual stress liner approach may be efficiently applied to semiconductor devices of the 45 nm technology and beyond.
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