发明授权
US08338894B2 Increased depth of drain and source regions in complementary transistors by forming a deep drain and source region prior to a cavity etch
有权
通过在腔蚀刻之前形成深漏极和源极区，增加互补晶体管中的漏极和源极区的深度
- 专利标题： Increased depth of drain and source regions in complementary transistors by forming a deep drain and source region prior to a cavity etch
- 专利标题（中）： 通过在腔蚀刻之前形成深漏极和源极区，增加互补晶体管中的漏极和源极区的深度
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申请号： US12693692申请日： 2010-01-26
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公开(公告)号： US08338894B2公开(公告)日： 2012-12-25
- 发明人: Uwe Griebenow , Jan Hoentschel , Sven Beyer
- 申请人： Uwe Griebenow , Jan Hoentschel , Sven Beyer
- 申请人地址： US TX Austin
- 专利权人： Advanced Micro Devices, Inc.
- 当前专利权人： Advanced Micro Devices, Inc.
- 当前专利权人地址： US TX Austin
- 代理机构： Williams, Morgan & Amerson
- 优先权： DE102009006800 20090130
- 主分类号： H01L27/092
- IPC分类号： H01L27/092 ; H01L21/8238
摘要：
Deep drain and source regions of an N-channel transistor may be formed through corresponding cavities, which may be formed together with cavities of a P-channel transistor, wherein the lateral offsets of the cavities may be adjusted on the basis of an appropriate reverse spacer regime. Consequently, the dopant species in the N-channel transistor extends down to a specific depth, for instance down to the buried insulating layer of an SOI device, while at the same time providing an efficient strain-inducing mechanism for the P-channel transistor with a highly efficient overall manufacturing process flow.
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