发明授权
- 专利标题: Vertical-type semiconductor device
- 专利标题(中): 垂直型半导体器件
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申请号: US12872270申请日: 2010-08-31
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公开(公告)号: US08344385B2公开(公告)日: 2013-01-01
- 发明人: Young-Hoo Kim , Hyo-San Lee , Sang-Won Bae , Bo-Un Yoon , Kun-Tack Lee
- 申请人: Young-Hoo Kim , Hyo-San Lee , Sang-Won Bae , Bo-Un Yoon , Kun-Tack Lee
- 申请人地址: KR
- 专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人地址: KR
- 代理机构: Myers Bigel Sibley & Sajovec, P.A.
- 优先权: KR10-2009-0092258 20090929
- 主分类号: H01L29/06
- IPC分类号: H01L29/06 ; H01L29/792
摘要:
In a vertical-type non-volatile memory device, an insulation layer pattern is provided on a substrate, the insulation layer pattern having a linear shape. Single-crystalline semiconductor patterns are provided on the substrate to make contact with both sidewalls of the insulation layer pattern, the single-crystalline semiconductor patterns having a pillar shape that extends in a vertical direction relative to the substrate. A tunnel oxide layer is provided on the single-crystalline semiconductor pattern. A lower electrode layer pattern is provided on the tunnel oxide layer and on the substrate. A plurality of insulation interlayer patterns is provided on the lower electrode layer pattern, the insulation interlayer patterns being spaced apart from one another by a predetermined distance along the single-crystalline semiconductor pattern. A charge-trapping layer and a blocking dielectric layer are sequentially formed on the tunnel oxide layer between the insulation interlayer patterns. A plurality of control gate patterns is provided on the blocking dielectric layer between the insulation interlayer patterns. An upper electrode layer pattern is provided on the tunnel oxide layer and on the uppermost insulation interlayer pattern.
公开/授权文献
- US20110073866A1 VERTICAL-TYPE SEMICONDUCTOR DEVICE 公开/授权日:2011-03-31