A reconfigurable hardware architecture, in the form of a System-on-Chip 1, includes an ASIC (19) and an embedded FPGA (18) which define static and reconfigurable parts of an IC architecture (15) respectively. Incoming Ethernet, or other format, packets are applied to a packet filter (14), which detects those packets containing reconfiguration data. The reconfiguration data is used to update the FPGA (18).