A shadow mask for patterning a substrate during a semiconductor process. In one implementation, a method for performing a Physical vapor deposition (PVD) on a substrate is provided. The method includes placing a substrate on a susceptor disposed below one or more PVD guns and below a plasma shield assembly having an aperture piece comprising a bellows and a shadow mask coupled to a bottom side of the bellows, the aperture piece detachably coupled to the plasma shield assembly, wherein a region defined between sides of the bellows is smaller than a width of the substrate. The method includes lowering the bellows toward the substrate to place the shadow mask in contact with the substrate and depositing a material on an isolated region on the substrate through the shadow mask.