A method for fabricating a TFT array substrate includes following steps. A gate pattern and a first pad pattern are formed on a substrate. A gate insulation layer and a semiconductor layer covering the two patterns are sequentially formed. A patterned photoresist layer having different resist blocks is formed, and patterns and thicknesses of the resist blocks in different regions are adjusted. The semiconductor layer and the gate insulation layer above the first pad pattern are removed through performing an etching process and reducing a thickness of the patterned photoresist layer. After removing the patterned photoresist layer, a source pattern, a drain pattern, and a second pad pattern electrically connected to the first pad pattern are formed. A patterned passivation layer is formed on the gate insulation layer and has a second opening exposing the source pattern or the drain pattern and a third opening exposing the second pad pattern.