Invention Grant
- Patent Title: High-k metal gate CMOS patterning method
- Patent Title (中): 高k金属栅极CMOS图案化方法
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Application No.: US12536629Application Date: 2009-08-06
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Publication No.: US08349680B2Publication Date: 2013-01-08
- Inventor: Kong-Beng Thei , Harry Chuang , Ryan Chia-Jen Chen , Su-Chen Lai , Yi-Shien Mor , Yi-Hsing Chen , Gary Shen , Yu Chao Lin
- Applicant: Kong-Beng Thei , Harry Chuang , Ryan Chia-Jen Chen , Su-Chen Lai , Yi-Shien Mor , Yi-Hsing Chen , Gary Shen , Yu Chao Lin
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/8238
- IPC: H01L21/8238

Abstract:
The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a first metal layer over the capping layer, the first metal layer having a first work function, forming a mask layer over the first metal layer in the first active region, removing the first metal layer and at least a portion of the capping layer in the second active region using the mask layer, and forming a second metal layer over the partially removed capping layer in the second active region, the second metal layer having a second work function.
Public/Granted literature
- US20100048013A1 NOVEL HIGH-K METAL GATE CMOS PATTERNING METHOD Public/Granted day:2010-02-25
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