- Patent Title: Self-aligned silicide formation on source/drain through contact via
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Application No.: US13070702Application Date: 2011-03-24
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Publication No.: US08349718B2Publication Date: 2013-01-08
- Inventor: Yoshihiro Uozumi
- Applicant: Yoshihiro Uozumi
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Turocy & Watson, LLP
- Main IPC: H01L21/28
- IPC: H01L21/28

Abstract:
According to certain embodiments, a silicide layer is formed after the fabrication of a functional gate electrode using a gate-last scheme. An initial semiconductor structure has at least one impurity regions formed on a semiconductor substrate, a sacrifice film formed over the impurity region, an isolation layer formed over the sacrifice film and a dielectric layer formed over the isolation film. A via is patterned into the dielectric layer of the initial semiconductor structure and through the thickness of the isolation layer such that a contact opening is formed in the isolation layer. The sacrifice film underlying the isolation layer is then removed leaving a void space underlying the isolation layer. Then, a metal silicide precursor is placed within the void space, and the metal silicide precursor is converted to a silicide layer through an annealing process.
Public/Granted literature
- US20120241963A1 SELF-ALIGNED SILICIDE FORMATION ON SOURCE/DRAIN THROUGH CONTACT VIA Public/Granted day:2012-09-27
Information query
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