发明授权
US08349740B2 Reduced topography-related irregularities during the patterning of two different stress-inducing layers in the contact level of a semiconductor device
有权
在半导体器件的接触电平中的两个不同的应力感应层的图案化期间减少了与地形相关的不规则性
- 专利标题： Reduced topography-related irregularities during the patterning of two different stress-inducing layers in the contact level of a semiconductor device
- 专利标题（中）： 在半导体器件的接触电平中的两个不同的应力感应层的图案化期间减少了与地形相关的不规则性
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申请号： US12623493申请日： 2009-11-23
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公开(公告)号： US08349740B2公开(公告)日： 2013-01-08
- 发明人: Ralf Richter
- 申请人： Ralf Richter
- 申请人地址： KY Grand Cayman
- 专利权人： GLOBALFOUNDRIES Inc.
- 当前专利权人： GLOBALFOUNDRIES Inc.
- 当前专利权人地址： KY Grand Cayman
- 代理机构： Williams, Morgan & Amerson, P.C.
- 优先权： DE102008059649 20081126
- 主分类号： H01L21/311
- IPC分类号： H01L21/311
摘要：
In sophisticated semiconductor devices, stress-inducing materials may be provided above the basic transistor devices without any etch control or etch stop materials, thereby enabling an efficient de-escalation of the surface topography, in particular above field regions including closely spaced polysilicon lines. Furthermore, an additional stress-inducing material may be provided on the basis of the superior surface topography, thereby providing a highly efficient strain-inducing mechanism in performance-driven transistor elements.
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