A structure of an output stage includes a first electrode, a second electrode, a third electrode, multiple first auxiliary electrodes connected to the first electrode, multiple second auxiliary electrodes and multiple third auxiliary electrodes both connected to the second electrode, multiple fourth auxiliary electrodes connected to the third electrode, multiple first transistors and multiple second transistors. The widths of each the first auxiliary electrode and each the fourth auxiliary electrode are inversely proportional to the distance thereof respectively from the first electrode and the third electrode. The width of each of the second auxiliary electrodes and the third auxiliary electrodes is inversely proportional to the distance thereof from the second electrode. The first and second auxiliary electrodes are electrically connected to each other respectively through the turned-on first transistors. The third and fourth auxiliary electrodes are electrically connected to each other respectively through the turned-on second transistors.