Invention Grant
- Patent Title: Techniques for placement of active and passive devices within a chip
- Patent Title (中): 有源和无源器件放置在芯片内的技术
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Application No.: US13231084Application Date: 2011-09-13
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Publication No.: US08350358B2Publication Date: 2013-01-08
- Inventor: Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Matthew Nowak
- Applicant: Jonghae Kim , Shiqun Gu , Brian Matthew Henderson , Thomas R. Toms , Matthew Nowak
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Michelle Gallardo; Nicholas J. Pauley; Jonathan T. Velasco
- Main IPC: H01L29/00
- IPC: H01L29/00

Abstract:
A semiconductor die includes a semiconductive substrate layer with first and second sides, a metal layer adjacent the second side of the semiconductive substrate layer, one or more active devices in an active layer on the first side of the semiconductive substrate layer; and a passive device in the metal layer in electrical communication with the active layer. The passive device can electrically couple to the active layer with through silicon vias (TSVs).
Public/Granted literature
- US20120001297A1 Techniques for Placement of Active and Passive Devices within a Chip Public/Granted day:2012-01-05
Information query
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