Invention Grant
US08350361B2 Semiconductor element having a conductive via and method for making the same and package having a semiconductor element with a conductive via
有权
具有导电通孔的半导体元件及其制造方法以及具有导电通孔的半导体元件的封装
- Patent Title: Semiconductor element having a conductive via and method for making the same and package having a semiconductor element with a conductive via
- Patent Title (中): 具有导电通孔的半导体元件及其制造方法以及具有导电通孔的半导体元件的封装
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Application No.: US12830964Application Date: 2010-07-06
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Publication No.: US08350361B2Publication Date: 2013-01-08
- Inventor: Chi-Tsung Chiu , Ying-Te Ou , Meng-Jen Wang
- Applicant: Chi-Tsung Chiu , Ying-Te Ou , Meng-Jen Wang
- Applicant Address: TW Kaohsiung
- Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee: Advanced Semiconductor Engineering, Inc.
- Current Assignee Address: TW Kaohsiung
- Agency: McCracken & Frank LLC
- Priority: TW98132084A 20090923
- Main IPC: H01L29/40
- IPC: H01L29/40

Abstract:
The present invention relates to a semiconductor element having a conductive via and a method for making the same and a package having a semiconductor element with a conductive via. The semiconductor element includes a silicon chip and at least one conductive via. The silicon chip includes a silicon substrate and an active circuit layer. The active circuit layer is disposed on a second surface of the silicon substrate, and has at least one metal layer. The conductive via penetrates the silicon substrate, and includes a conductive metal. The conductive metal electrically connects to the metal layer of the active circuit layer, and a surface of the conductive metal is exposed to the outside of a first surface of the silicon substrate. Therefore, a chip is able to be directly stacked on the semiconductor element without forming a passivation layer and a redistribution layer on the first surface of the silicon substrate, and the process is simplified and the manufacturing cost is decreased.
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