Invention Grant
- Patent Title: Mitigation of well proximity effect in integrated circuits
- Patent Title (中): 减轻集成电路中的良好邻近效应
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Application No.: US13005680Application Date: 2011-01-13
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Publication No.: US08350365B1Publication Date: 2013-01-08
- Inventor: Yun Wu , Hong-Tsz Pan , Qi Lin , Bang-Thu Nguyen
- Applicant: Yun Wu , Hong-Tsz Pan , Qi Lin , Bang-Thu Nguyen
- Applicant Address: US CA San Jose
- Assignee: Xilinx, Inc.
- Current Assignee: Xilinx, Inc.
- Current Assignee Address: US CA San Jose
- Agent Scott Hewett; LeRoy D. Maunu
- Main IPC: H01L21/4763
- IPC: H01L21/4763
Abstract:
A hard implantation mask layer is formed on a semiconductor wafer. An etch mask layer is formed on the hard implantation mask layer and patterned. The hard implantation mask layer is etched to form a well implantation pattern and ions are implanted into the semiconductor wafer to form wells in the semiconductor wafer, in areas where the semiconductor wafer is not covered by the well implantation mask.
Information query
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