Invention Grant
US08350384B2 Semiconductor device and method of forming electrical interconnect with stress relief void
有权
形成具有应力消除空隙的电互连的半导体器件和方法
- Patent Title: Semiconductor device and method of forming electrical interconnect with stress relief void
- Patent Title (中): 形成具有应力消除空隙的电互连的半导体器件和方法
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Application No.: US12963934Application Date: 2010-12-09
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Publication No.: US08350384B2Publication Date: 2013-01-08
- Inventor: Rajendra D. Pendse
- Applicant: Rajendra D. Pendse
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Ltd.
- Current Assignee: STATS ChipPAC, Ltd.
- Current Assignee Address: SG Singapore
- Agency: Atkins & Associates, P.C
- Agent Robert D. Atkins
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/44

Abstract:
A semiconductor device has a semiconductor die with a plurality of tapered bumps formed over a surface of the semiconductor die. The tapered bumps can have a non-collapsible portion and collapsible portion. A plurality of conductive traces is formed over a substrate with interconnect sites. A masking layer is formed over the substrate with openings over the conductive traces. The tapered bumps are bonded to the interconnect sites so that the tapered bumps contact the mask layer and conductive traces to form a void within the opening of the mask layer over the substrate. The substrate can be non-wettable to aid with forming the void in the opening of the masking layer. The void provides thermally induced stress relief. Alternatively, the masking layer is sufficiently thin to avoid the tapered interconnect structures contacting the mask layer. An encapsulant or underfill material is deposited between the semiconductor die and substrate.
Public/Granted literature
- US20110121464A1 Semiconductor Device and Method of Forming Electrical Interconnect with Stress Relief Void Public/Granted day:2011-05-26
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