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US08350385B2 Reduced bottom roughness of stress buffering element of a semiconductor component 有权
降低半导体部件的应力缓冲元件的底部粗糙度

  • Patent Title: Reduced bottom roughness of stress buffering element of a semiconductor component
  • Patent Title (中): 降低半导体部件的应力缓冲元件的底部粗糙度
  • Application No.: US12670562
    Application Date: 2008-07-15
  • Publication No.: US08350385B2
    Publication Date: 2013-01-08
  • Inventor: Hendrik Hochstenbach
  • Applicant: Hendrik Hochstenbach
  • Applicant Address: NL Eindhoven
  • Assignee: NXP B.V.
  • Current Assignee: NXP B.V.
  • Current Assignee Address: NL Eindhoven
  • Priority: EP07113388 20070730
  • International Application: PCT/IB2008/052840 WO 20080715
  • International Announcement: WO2009/016531 WO 20090205
  • Main IPC: H01L23/485
  • IPC: H01L23/485
Reduced bottom roughness of stress buffering element of a semiconductor component
Abstract:
The present invention relates to a stress buffering package (49) for a semiconductor component, with a semiconductor substrate (52); an I/O pad (54), electrically connected to the semiconductor substrate (52); a stress buffering element (74) for absorbing stresses, electrically connected to the I/O pad (54); an underbump metallization (70), electrically connected to the stress buffering element (74); a solder ball (60), electrically connected to the underbump metallization (70); a metal element (61) between the solder ball (60) and the semiconductor substrate (52); a passivation layer (56, 58), which protects the semiconductor substrate (52) and the metal element (61) and which at least partially exposes the I/O pad (54); characterized in that a roughness of an interface between the stress buffering element (74) and the passivation layer (56, 58) is lower than a roughness of an interface between the metal element (61) and the passivation layer (56, 58). Furthermore the invention relates a method for manufacturing a stress buffering package (49) for a semiconductor component.
Abstract(Chinese):

本发明涉及一种具有半导体衬底（52）的用于半导体部件的应力缓冲封装（49）。 电连接到半导体衬底（52）的I / O焊盘（54） 用于吸收与I / O焊盘（54）电连接的应力的应力缓冲元件（74）。 与应力缓冲元件（74）电连接的底部灌注金属化（70）; 电连接到下凸块金属化（70）的焊球（60）; 在所述焊球（60）和所述半导体基板（52）之间的金属元件（61） 钝化层（56,58），其保护所述半导体衬底（52）和所述金属元件（61）并且至少部分地暴露所述I / O焊盘（54）; 其特征在于，所述应力缓冲元件（74）和所述钝化层（56,58）之间的界面的粗糙度低于所述金属元件（61）与所述钝化层（56,58）之间的界面的粗糙度。 此外，本发明涉及制造用于半导体部件的应力缓冲封装（49）的方法。

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