Invention Grant
- Patent Title: Component built-in wiring board and manufacturing method of component built-in wiring board
- Patent Title (中): 组件内置线路板及组件内置线路板的制造方法
-
Application No.: US12740694Application Date: 2008-10-29
-
Publication No.: US08350388B2Publication Date: 2013-01-08
- Inventor: Kenji Sasaoka
- Applicant: Kenji Sasaoka
- Applicant Address: JP Tokyo
- Assignee: Dai Nippon Printing Co., Ltd.
- Current Assignee: Dai Nippon Printing Co., Ltd.
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JPP2007-284754 20071101; JPP2007-302883 20071122; JPP2007-322062 20071213
- International Application: PCT/JP2008/069678 WO 20081029
- International Announcement: WO2009/057654 WO 20090507
- Main IPC: H01L23/485
- IPC: H01L23/485

Abstract:
Disclosed is a component built-in wiring board, including a first insulating layer; a second insulating layer positioned in a laminated state on the first insulating layer; a semiconductor element buried in the second insulating layer, having a semiconductor chip with terminal pads and having surface mounting terminals arrayed in a grid shape connected electrically with the terminal pads; an electric/electronic component further buried in the second insulating layer; a wiring pattern sandwiched between the first insulating layer and the second insulating layer, including a first mounting land for the semiconductor element and a second mounting land for the electric/electronic component; a first connecting member connecting electrically the surface mounting terminal of the semiconductor element with the first mounting land; and a second connecting member connecting electrically the terminals of the electric/electronic component with the second mounting land, made of a same material as a material of the first connecting member.
Public/Granted literature
- US20100301473A1 COMPONENT BUILT-IN WIRING BOARD AND MANUFACTURING METHOD OF COMPONENT BUILT-IN WIRING BOARD Public/Granted day:2010-12-02
Information query
IPC分类: