A clock loss detection circuit is presented. The clock loss detection has two edge detection circuits and a clock loss detect counter circuit. Each edge detection circuit includes a reset signal circuit that generates a reset signal in response to a transition of a clock signal, and the reset signal circuit is connected to a clock input of the edge detection circuit. Each edge detection circuit also has a multiplexer connected to the reset signal circuit, and another multiplexer connected to the clock input. The clock loss detect counter circuit is connected to the edge detection circuits so that the clock loss detect counter circuit receives the reset signal from the second edge detection circuit and the clock signal from the first edge detection circuit.