A scaling engine, blending mechanism, memory controller, frame buffer and video driver are included within a semiconductor, such as a Field Programmable Gate Array (FPGA), to provide broadcasting of signals at a high resolution format by combining two or more low resolution video signals to create a high resolution signal in real-time High Definition format, such as 1080p. The high resolution signals can be concurrently displayed as one or more image areas on a display device in any contemplated size, number and arrangement.