Invention Grant
- Patent Title: CMOS SRAM memory cell with improved N/P current ratio
- Patent Title (中): 具有改善N / P电流比的CMOS SRAM存储单元
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Application No.: US12624291Application Date: 2009-11-23
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Publication No.: US08351248B1Publication Date: 2013-01-08
- Inventor: Michael J. Hart
- Applicant: Michael J. Hart
- Applicant Address: US CA San Jose
- Assignee: Xilinx, Inc.
- Current Assignee: Xilinx, Inc.
- Current Assignee Address: US CA San Jose
- Agent Scott Hewett; LeRoy D. Maunu
- Main IPC: G11C11/00
- IPC: G11C11/00
Abstract:
A memory cell in an integrated circuit has a first PMOS transistor formed in N-type semiconductor material and a first NMOS transistor formed in P-type semiconductor material. A well bias line coupled to the N-type semiconductor material or to the P-type semiconductor material provides a well bias voltage not equal to the PMOS bias voltage or to the NMOS bias voltage to reverse body-bias the PMOS transistor or to forward body-bias the NMOS transistor.
Information query
