Invention Grant
US08351263B2 Method circuit and system for operating an array of non-volatile memory (“NVM”) cells and a corresponding NVM device
失效
用于操作非易失性存储器（NVM）单元阵列和相应的NVM器件的方法电路和系统
- Patent Title: Method circuit and system for operating an array of non-volatile memory (“NVM”) cells and a corresponding NVM device
- Patent Title (中): 用于操作非易失性存储器（NVM）单元阵列和相应的NVM器件的方法电路和系统
-
Application No.: US12505491Application Date: 2009-07-19
-
Publication No.: US08351263B2Publication Date: 2013-01-08
- Inventor: Aner Arussi
- Applicant: Aner Arussi
- Applicant Address: IL Rosh Ha Ayin
- Assignee: Infinite Memory Ltd.
- Current Assignee: Infinite Memory Ltd.
- Current Assignee Address: IL Rosh Ha Ayin
- Agency: Professional Patent Solutions
- Agent Vladimir Sherman
- Main IPC: G11C16/04
- IPC: G11C16/04
Abstract:
Disclosed is a method, circuit and system for determining a Lowest Operative Threshold Voltage Level for one or more cell segments/blocks/sets of a NVM array and a corresponding device, adapted to compare substantially native state NVM cells in a block of cells against one or more reference cells/structures or offset values, and to maintain a read error count.
Public/Granted literature
Information query
