Invention Grant
- Patent Title: Apparatuses and methods to reduce power consumption in digital circuits
- Patent Title (中): 降低数字电路功耗的装置和方法
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Application No.: US12830151Application Date: 2010-07-02
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Publication No.: US08351272B2Publication Date: 2013-01-08
- Inventor: Harish N. Venkata
- Applicant: Harish N. Venkata
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Main IPC: G11C11/34
- IPC: G11C11/34

Abstract:
An apparatus and method for reducing power consumption in digital circuits, particularly circuits including a charge pump. A driver may selectively drive a signal line, such as a memory device wordline, between a first voltage, which may be a voltage generated by the charge pump, and a different second voltage. A coupling circuit may be coupled between the signal line and the charge pump to selectively couple the signal line to the charge pump responsive to the signal line being driven from the first voltage to the second voltage. For example, the first voltage may be a voltage generated by the charge pump, and the second voltage may be a voltage having a lesser magnitude. As a result, the voltage on the signal line may be discharged into the charge pump when the voltage of the signal line transitions from the first voltage to the second voltage.
Public/Granted literature
- US20120001682A1 APPARATUSES AND METHODS TO REDUCE POWER CONSUMPTION IN DIGITAL CIRCUITS Public/Granted day:2012-01-05
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