发明授权
- 专利标题: Apparatuses and methods to reduce power consumption in digital circuits
- 专利标题(中): 降低数字电路功耗的装置和方法
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申请号: US12830151申请日: 2010-07-02
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公开(公告)号: US08351272B2公开(公告)日: 2013-01-08
- 发明人: Harish N. Venkata
- 申请人: Harish N. Venkata
- 申请人地址: US ID Boise
- 专利权人: Micron Technology, Inc.
- 当前专利权人: Micron Technology, Inc.
- 当前专利权人地址: US ID Boise
- 代理机构: Dorsey & Whitney LLP
- 主分类号: G11C11/34
- IPC分类号: G11C11/34
摘要:
An apparatus and method for reducing power consumption in digital circuits, particularly circuits including a charge pump. A driver may selectively drive a signal line, such as a memory device wordline, between a first voltage, which may be a voltage generated by the charge pump, and a different second voltage. A coupling circuit may be coupled between the signal line and the charge pump to selectively couple the signal line to the charge pump responsive to the signal line being driven from the first voltage to the second voltage. For example, the first voltage may be a voltage generated by the charge pump, and the second voltage may be a voltage having a lesser magnitude. As a result, the voltage on the signal line may be discharged into the charge pump when the voltage of the signal line transitions from the first voltage to the second voltage.
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