Invention Grant
- Patent Title: Method for operating semiconductor memory device
- Patent Title (中): 操作半导体存储器件的方法
-
Application No.: US13039557Application Date: 2011-03-03
-
Publication No.: US08351277B2Publication Date: 2013-01-08
- Inventor: Yoshimasa Mikajiri , Shigeto Oota , Masaru Kito , Ryouhei Kirisawa
- Applicant: Yoshimasa Mikajiri , Shigeto Oota , Masaru Kito , Ryouhei Kirisawa
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2010-049415 20100305
- Main IPC: G11C16/04
- IPC: G11C16/04

Abstract:
According to one embodiment, a method is disclosed for operating a semiconductor memory device. The semiconductor memory device includes a substrate, a stacked body, a memory film, a channel body, a select transistor, and a wiring. The method can boost a potential of the channel body by applying a first erase potential to the wiring, the select gate, and the word electrode layer. In addition, after the boosting of the potential of the channel body, with the wiring and the select gate maintained at the first erase potential, the method can decrease a potential of the word electrode layer to a second erase potential lower than the first erase potential.
Public/Granted literature
- US20110216604A1 METHOD FOR OPERATING SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2011-09-08
Information query