Invention Grant
- Patent Title: Jam latch for latching memory array output data
- Patent Title (中): 用于锁存存储器阵列输出数据的卡锁
-
Application No.: US12822038Application Date: 2010-06-23
-
Publication No.: US08351278B2Publication Date: 2013-01-08
- Inventor: Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar J. Vora
- Applicant: Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar J. Vora
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Cantor Colburn LLP
- Agent William A. Kinnaman, Jr.
- Main IPC: G11C7/10
- IPC: G11C7/10

Abstract:
A jam latch device for a data node includes a feed forward inverter having an input coupled to the data node; a feedback inverter having an input connected to an output of the feed forward inverter with an output of the feedback inverter connected to the data node; an isolation device that selectively decouples the feedback inverter from a power supply rail, the isolation device controlled by a clock signal of a reset device that resets the data node to a first logic state such that decoupling of the feedback inverter from the power supply rail coincides with resetting the data node to the first logic state; and a margin test device that selectively increases pull down strength of the feedback inverter.
Public/Granted literature
- US20110317496A1 JAM LATCH FOR LATCHING MEMORY ARRAY OUTPUT DATA Public/Granted day:2011-12-29
Information query