A two-phase return-to-zero asynchronous transceiver is provided. The two-phase return-to-zero asynchronous transceiver is designed for on-chip interconnects. The transceiver includes a multi-stage transceiver arranged in a dual rail configuration, along with a weak keeper for each stage, a data driver for each stage, and an enable control circuit for selectively enabling the data driver, such that the data driver outputs data to a subsequent stage of the multi-stage transceiver. The enable control circuit further utilizes a handshaking protocol, which may be implemented at 0.13 μm and 1.2 Volts. The transceiver circuit achieves a throughput of approximately 3 Gb/s with wire lengths of approximately 100 μm.