A circuit for detecting a clock has a plurality of first transmission elements, a plurality of first exclusive OR gates and a first AND gate. Each first transmission element is coupled to a last first transmission element for receiving output data, and the data received by each first transmission element is transmitted to an input terminal of a next first transmission element. In addition, the input of a first transmission element is coupled to a clock source for receiving a predetermined clock signal of which a frequency is less than a frequency of a local clock signal. Furthermore, the first and second input terminals of a kth exclusive OR gate are coupled to output terminals of a kth and a (k+1)th first transmission elements, wherein k is an integer greater than 0 smaller than a total number of the first transmission elements.